1. Field of the Invention
The present invention generally relates to the forming of diodes having low capacitance and low series resistance in semiconductor wafers. More specifically, the present invention relates to the forming of diodes having all their contacts on the front surface side. Such diodes are useful in certain high-frequency (radio-frequency) applications.
2. Discussion of the Related Art
A method for manufacturing a diode having reduced capacitance is described hereafter in relation with FIG. 1 in the case of a PIN-type diode.
A heavily-doped semiconductor substrate 1, generally single-crystal silicon, of a first conductivity type, for example, N-type, is used. The method starts with the epitaxial growth, on substrate 1, of a layer 2 of same conductivity type N as substrate 1, but more lightly doped. A heavily-doped layer 3 of the opposite conductivity type, for example, P-type, is then formed. To exhibit a reduced capacitance, the diode must have a reduced surface area. The diode surface area is limited by digging a peripheral groove 4. Groove 4 is dug to at least reach substrate 1. Groove 4 generally has a depth at least equal to the height of layers 2 and 3. The entire structure is then coated with an insulating layer 5, typically silicon oxide. Insulating layer 5 is then opened in the diode region delimited by groove 4. A conductive material, typically aluminum, is deposited and etched, to form an anode contact 6 with layer 3. A cathode contact (not shown) is subsequently formed by a metallization on the rear surface of substrate 1.
To obtain a front surface assembly diode, it could be devised to directly form a cathode contact by opening, as illustrated in FIG. 1, insulating layer 5 outside of the region delimited by groove 4, to partially expose layer 3. Layer 5 would then be used as an implantation mask to form a heavily-doped region 7 of the same conductivity type, N, as substrate 1. Region 7 would be formed sufficiently deeply to reach substrate 1 and form a cathode contacting area. A cathode contact 8 would then be formed on region 7, at the front surface, at the same time as anode contact 6.
However, the forming of deep heavily-doped region 7 requires an additional anneal. To obtain a PIN diode of good quality, the transition between substrate 1 and layer 2 and the junction between layers 2 and 3 must be particularly steep. The diffusion anneal would adversely affect the diode characteristics (capacitance, series resistance, breakdown voltage).